A NAND flash memory (hereinafter, simply referred to as a flash memory or an FM) will be described. A flash memory cannot directly rewrite stored data and requires an erase process. A block is an erase unit of data and a page is a write/read unit of data. Hereinafter, unless otherwise specified, a simply-described block/page implies that the block/page belongs to a flash memory. A plurality of pages are provided in a single block.
When a flash memory device that is a storage device using a flash memory rewrites data, the flash memory device first loads stored valid data to a storage device without an erase unit such as a DRAM (Dynamic Random Access Memory) and updates a necessary location. Next, the flash memory device performs an erase process on a block in which the data had originally been stored. Finally, the flash memory device writes data to the erased block. In this manner, rewriting data to a flash memory is accompanied by erasing data from each block. However, the time required to erase one block's worth of data in the flash memory is longer than the time required to write one page's worth of data and, therefore, with a system which erases one block's worth of data every time one page's worth of data is rewritten, data rewrite performance of the flash memory declines.
To address such problems, a flash memory device additionally writes update data to an unused area in a rewrite operation of data. Accordingly, at a time point where data is updated, a block need no longer be erased. In addition, to accommodate such additional write operations, a flash memory device usually possesses a physical area equal to or larger than a capacity disclosed to a higher-level apparatus as an update area. However, since an increase in an amount of rewritten data may result in depleting the update area in the flash memory device, data logically invalidated by the update of data must be erased to change the storage area into a reusable state (a free area). In consideration thereof, a block recovery process is known in which a flash memory device copies only valid data in a block including invalid data to an unused area and, after invalidating all of the data in the block, erases the copy source block to create a free area. Hereinafter, this process will be referred to as reclamation. Reclamation may also be abbreviated as RC. By executing reclamation on a block with a high invalid data rate as a target, a free area can be created in an efficient manner.
Characteristics of a flash memory degrade with use. Degradation is conceivably correlated with the number of cell erases and, generally, SSD (Solid State Disk) vendors present a maximum number of erases for which quality of data retention characteristics can be guaranteed. While degradation occurs in cell units, since erases promote degradation, a rate of progress of degradation of cells in a block is uniformized to a certain degree. When rewrites of data concentrate on a specified block and the block becomes unusable due to an increase in the number of erases, in a worst-case scenario, a problem occurs in that, a part of the blocks reaching a rewrite limit and becoming unusable prevents capacity of a flash memory device from being satisfied despite other blocks being in a sound condition. In consideration thereof, a known leveling process of degradation of each block is performed so that degradation does not concentrate on a specified block. This process is referred to as wear leveling and may hereinafter be abbreviated as WL.
In a flash memory, a read error rate increases over time even with a page once written to. Such an error is referred to as a retention error. To avoid a retention error, a process is known in which a page after a certain period of time has elapsed since being written to is copied to another page. This process is referred to as a refresh. Refresh may also be abbreviated as RF. Even when performing a refresh, the issue of leveling described earlier and an effect on performance must be taken into consideration.
In order to conceal a data erase time and to level the number of data erases described above, when writing data, a flash memory device performs a logical-physical address translation process for translating a logical address into a physical address. A flash memory device includes one or more FM chips and a device controller which controls read and write of data with respect to the FM chips. The device controller performs the logical-physical address translation process. Furthermore, the device controller stores information for the logical-physical address translation process in the form of a logical-physical address translation table. Hereinafter, the logical-physical address translation process may be referred to as a logical-physical translation and the logical-physical address translation table may be referred to as a logical-physical translation table.
The logical-physical translation plays an important role in efficiently using a flash memory. When using a logical-physical translation with a low degree of freedom, although a size of a logical-physical translation table can be suppressed, performance declines due to frequent occurrences of reclamation. On the other hand, when using a logical-physical translation with a high degree of freedom, the size of the logical-physical translation table becomes enormous and control cost increases significantly.
The wear leveling described earlier is realized by matching a determination of write frequency of data with a degree of degradation of each block. A minimum granularity of management of the write frequency of data is a unit of allocation to a physical storage area which is defined by logical-physical translation. While various logical-physical translation systems are being proposed in accordance with target operations, a system that is conceivably simple and efficient involves dividing a host address that is a logical address provided by a flash memory device to a higher-level apparatus by a fixed length and mapping the divided host address onto a physical address in a flat table. A logical unit of a division of the host address is referred to as a logical page while a page of a flash memory is referred to as a physical page in order to distinguish the page from a logical page. Although advantages such as improved manageability and enhanced read-response performance may conceivably be gained by matching a size of a logical page to that of a physical page, a more elaborate arrangement can conceivably be realized by managing a logical page size to be smaller than a physical page size or, conversely, setting the logical page size to be larger than the physical page size in order to reduce an amount of information necessary for management.
Since a logical-physical translation table is inevitably referred to during I/O, the logical-physical translation table is generally stored in a storage medium with less access latency such as a DRAM.
PTL 1 discloses a controller of a flash memory device allocating a logical block with a low erase frequency to a physical block with a small number of erases.